The starting point for our activity is professor Vladutiu's expertise and long time experience in teaching computer arithmetic, memory hierarchy, and processor design. Our aim is to investigate possible improvements for arithmetic algorithms, together with their corresponding hardware designs.

But the most important attempt is to link these purely classical hardware insights to new fields like reconfigurable (perhaps even evolvable) hardware and quantum computing. Most hardware arithmetic devices are designed for the worst-case scenario; however, this is not really necessary if special designs, which are appropriate for the given operand patterns, are used (by reconfigurable hardware RHW techniques). Therefore, our Computer Architecture and Design group launches a new and exciting ACSA research project:
"Fast Multipliers/Dividers using Reconfigurable Hardware".
Another parameter to optimize by reconfigurable solutions is the power consumption.

The most important quantum algorithm is Shor’s algorithm for factoring large integers, which requires arithmetic circuits for modulo exponentiation. As building blocks, efficient quantum adders, multipliers and dividers must be available. The already proposed quantum arithmetic designs are inspired from the classical designs but, unfortunately, not from the most advanced ones. Moreover, these designs are not taking into consideration vital aspects like the fault tolerance degree of the design. Thus, the second project is a comparison between the classical arithmetic designs and their quantum counterparts. The bottom line is to assess the opportunity of adopting a given classical design model into quantum circuitry.

• Design of arithmetic algorithms
• Arithmetic circuit design
• Low-power design
• Embedded systems and SoCs
• Reconfigurable computing